Current Issue : October - December Volume : 2017 Issue Number : 4 Articles : 5 Articles
In the era of Internet of Things, the battery life of edge devices must be extended\nfor sensing connection to the Internet. We aim to reduce the power\nconsumption of the microprocessor embedded in such devices by using a\nnovel dynamically reconfigurable accelerator. Conventional microprocessors\nconsume a large amount of power for memory access, in registers, and for the\ncontrol of the processor itself rather than computation; this decreases the\nenergy efficiency. Dynamically reconfigurable accelerators reduce such redundant\npower by computing in parallel on reconfigurable switches and\nprocessing element arrays (often consisting of an arithmetic logic unit (ALU)\nand registers). We propose a novel dynamically reconfigurable accelerator\nââ?¬Å?DYNaSTAââ?¬Â composed of a dynamically reconfigurable data path and static\nALU arrays. The static ALU arrays process instructions in parallel without\nregisters and improve energy efficiency. The dynamically reconfigurable data\npath includes registers and many switches dynamically reconfigured to resolve\noperand dependencies between instructions mapped on the static ALU array,\nand forwards appropriate operands to the static ALU array. Therefore, the\nDYNaSTA accelerator has more flexibility while improving the energy efficiency\ncompared with the conventional dynamically reconfigurable accelerators.\nWe simulated the power consumption of the proposed DYNaSTA accelerator\nand measured the fabricated chip. As a result, the power consumption\nwas reduced by 69% to 86%, and the energy efficiency improved 4.5 to 13\ntimes compared to a general RISC microprocessor....
We designed and developed a 24GHz surveillance FMCW (Frequency Modulated Continuous Wave) radar with a softwarereconfigurable\nbaseband.The developed radar system consists of transceiver, two selectable transmit antennas, eight parallel receive\nantennas, and a back-end module for data logging and to control the transceiver. The architecture of the developed radar system\ncan support various waveforms, gain control of receive amplifiers, and allow the selection of two transmit antennas. To do this,\nwe implemented the transceiver using a frequency synthesizer device and a two-step VGA (Variable Gain Amplifier) along with\nswitch-controlled transmit antennas. To support high speed implementation features along with good flexibility, we developed a\nback-end module based on a FPGA (Field Programmable Gate Array) with a parallel architecture for the real-time data logging\nof the beat signals received from a multichannel 24GHz transceiver. To verify the feasibility of the developed radar system, signal\nprocessing algorithms were implemented on a host PC. All measurements were carried out in an anechoic chamber to extract a 3D\nrange-Doppler-angle map and target detections.We expect that the developed software-reconfigurable radar system will be useful\nin various surveillance applications....
In modern SRAMbased Field Programmable Gate Arrays, a Look-Up Table (LUT) is the principal constituent logic element which\ncan realize every possible Boolean function. However, this flexibility of LUTs comes with a heavy area penalty. A part of this\narea overhead comes from the increased amount of configuration memory which rises exponentially as the LUT size increases.\nIn this paper, we first present a detailed analysis of a previously proposed FPGA architecture which allows sharing of LUTs memory\n(SRAM) tables among NPN-equivalent functions, to reduce the area as well as the number of configuration bits.We then propose\nseveral methods to improve the existing architecture. A new clustering technique has been proposed which packs NPN-equivalent\nfunctions together inside a Configurable Logic Block (CLB). We also make use of a recently proposed high performance Boolean\nmatching algorithm to perform NPN classification. To enhance area savings further, we evaluate the feasibility of more than two\nLUTs sharing the same SRAM table. Consequently, this work explores the SRAM table sharing approach for a range of LUT sizes\n(4ââ?¬â??7), while varying the cluster sizes (4ââ?¬â??16). Experimental results onMCNC benchmark circuits set show an overall area reduction\nof âË?¼7% while maintaining the same critical path delay....
There are many recent investigations on chaotic hidden attractors although hyperchaotic hidden attractor systems and their\nrelationships have been less investigated. In this paper, we introduce a hyperchaotic system which can change between hidden\nattractor and self-excited attractor depending on the values of parameters. Dynamic properties of these systems are investigated.\nFractional ordermodels of these systems are derived and their bifurcation with fractional orders is discussed. Field programmable\ngate array (FPGA) implementations of the systems with their power and resource utilization are presented....
Finite difference time domain (FDTD) method is a very poplar way of numerically solving partial differential equations. FDTD has\na low operational intensity so that the performances in CPUs and GPUs are often restricted by the memory bandwidth. Recently,\ndeeply pipelined FPGA accelerators have shown a lot of success by exploiting streaming data flows in FDTD computation. In spite\nof this success, many FPGA accelerators are not suitable for real-world applications that contain complex boundary conditions.\nBoundary conditions break the regularity of the data flow, so that the performances are significantly reduced. This paper proposes\nan FPGA accelerator that computes commonly used absorbing and periodic boundary conditions in many 3D FDTD applications.\nAccelerator is designed using a ââ?¬Å?C-likeââ?¬Â programming language called OpenCL (open computing language). As a result, the\nproposed accelerator can be customized easily by changing the software code. According to the experimental results, we achieved\nover 3.3 times and 1.5 times higher processing speed compared to the CPUs and GPUs, respectively. Moreover, the proposed\naccelerator ismore than 14 times faster compared to the recently proposed FPGA accelerators that are capable of handling complex\nboundary conditions....
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